For example, in a manufacturing process of an NAND type flash memory, a process for removing an Si-based film such as a silicon oxide film (SiO2 film) or a silicon nitride film (SiN film) which remains on a surface of a semiconductor wafer (hereinafter, referred to as “wafer”) by etching is carried out. FIGS. 1 and 2 show parts of the manufacturing process of the NAND type flash memory. First, as shown in FIG. 1A, a silicon oxide film 101 is formed on a single crystalline silicon substrate 100 by thermal oxidation method and, then, a polysilicon film 102 is laminated thereon by an LPCVD method or the like. Next, as shown in FIG. 1B, parts of the polysilicon film 102, the silicon oxide film 101 and the single crystalline silicon substrate 100 are etched by consecutively performing well-known anisotropic etching. As a consequence, grooves 105 are formed, and the devices are divided. Since each device is cut by the anisotropic etching, the silicon oxide film 101 serves as an insulating film 103 of each device, and the polysilicon film 102 serves as a floating gate 104 of each device. Further, the grooves 105 formed on the single crystalline silicon substrate 100 serve as shallow trench isolation (STI) regions.
As shown in FIG. 1C, a new silicon oxide film 106 is deposited so as to fill the grooves 105 and the spaces between the devices by an LPCVD method or the like. Next, the deposited silicon oxide film 106 is etched, the structure shown in FIG. 2A in which a partial sidewall 107 of a floating gate 104 is exposed is formed. Thereafter, as shown in FIG. 2B, an ONO insulating film 108 and a polysilicon film (control gate) 109 are laminated. Since the ONO insulating film 108 is laminated in a state where the partial sidewall 107 of the floating gate 104 is exposed, the contact area of the floating gate 104 and the ONO insulating film 108 is increased, and a write voltage applied to the control gate (the polysilicon film 109) in the case of writing data in a memory cell can be set to a low level. Here, as for the method for etching the silicon oxide film 106, wet etching using a liquid chemical, plasma etching using a reactive gas plasma or the like is conventionally known.
In the process for exposing the partial sidewall 107 of the floating gate 104 which is shown in FIG. 2A, the etching amount of the newly deposited silicon oxide film 106 determines a height of the exposed partial sidewall 107 of the floating gate 104, so that the etching amount needs to be controlled with high accuracy. If the etching amount of the silicon oxide film 106 is different from a design value in each device, the contact area of the floating gate 104 and the ONO insulating film 108 is changed. As a result, the reliability of the device deteriorates.
However, the wet etching has low controllability due to a high etching rate. Further, the plasma etching is disadvantageous in that it affects a film other than the Si-based film. Therefore, as for the method for selectively removing an Si-based film on a wafer surface with high accuracy, there is known a chemical removing process for chemically removing the Si-based film (see Patent Documents 1 and 2). In the chemical removing process, the Si-based film is transformed into a reaction product mainly made of ammonium fluorosilicate by supplying a gaseous mixture of a gas containing a halogen element and an alkaline gas into the processing chamber, and the reaction product is removed from the wafer by vaporizing (sublimating) the corresponding reaction product. In that case, hydrogen fluoride gas (HF) is used for the gas containing a halogen element, and ammonia gas (NH3) is used for the alkaline gas, for example.    Patent Document 1: Japanese Patent Application Publication No. 2008-160000    Patent Document 2: Japanese Patent Application Publication No. 2008-235311
The chemical removing process has high controllability since it has a lower removal rate compared to the wet processing. Moreover, the chemical removing process is advantageous in that it causes less effect on a film other than the Si-based film compared to the plasma etching process. On the contrary, the chemical removing process has a low removal rate for the Si-based film and hardly increases productivity.
Meanwhile, as for an apparatus for performing a COR (Chemical Oxide Removal) process for chemically removing an oxide, there is conventionally known an apparatus including a chemical processing chamber for performing a process for transforming an oxide film on a surface of a wafer into a reaction product at a comparatively low temperature and a thermal processing chamber for performing a process for removing the reaction product from the wafer by heating and sublimation at a comparatively high temperature, as described in Patent Document 1. However, the processing apparatus in which the chemical processing chamber and the thermal processing chamber are separately provided is scaled up since the number of the processing chambers is increased. Moreover, if the chemical processing chamber and the thermal processing chamber are separately provided, a transfer device for transferring a substrate therebetween is required and, also, transfer time is required.
Meanwhile, there is suggested a substrate processing apparatus for performing a process for transforming an oxide film on a wafer surface into a reaction product at a low temperature and then performing a process for removing the reaction product from the wafer by heating and sublimation in the same processing chamber, as described in Patent Document 2. However, even in the same processing chamber, a long period of time is required to change the temperature of the wafer, and it is difficult to increase the productivity.